1. Field of Invention
The invention relates to programming floating gate memory cells, and in particular to improved techniques of reading and writing of dual floating gate memory cells.
2. Discussion of Related Art
There are many commercially successful non-volatile memory products being used today, particularly in the form of small cards, which use an array of flash EEPROM cells. The basic architecture of an individual EEPROM memory cell includes source and drain diffusions, coupled by a channel, formed in a semiconducting substrate. The storage element itself is positioned above the channel, separated from it by a dielectric layer. This storage element is often referred to as a floating gate. Overlying the storage element there can be a select gate, used to address the individual cell for programming and reading.
Some designs include a split channel architecture, as described, for example, in U.S. Pat. No. 5,095,344, granted to E. Harari, which is incorporated herein by this reference in its entirety. In a split channel cell both the storage element and the select gate overlie the channel partially. This design has the advantage of simplicity, but the select gate performs the multiple functions of addressing the individual cells to be programmed or read, as well as the function of participating in the actual programming or reading of the cells as well.
Another design introduces an additional steering gate, positioned between the storage element and the select gate. The select gate continues to carry out the addressing function and even may contribute to the programming, but the primary programming and reading functions are performed by the steering gate, as described, for example, in U.S. Pat. No. 5,313,421, granted to D. Guterman et al., which is incorporated herein by this reference in its entirety.
Higher storage densities can be achieved by a dual cell design, as described, for example, in U.S. Pat. No. 5,712,180, granted to D. Guterman et al., which is incorporated herein by this reference in its entirety. There are two floating gates per cell in the dual cell architecture, overlying portions of the same channel. Corresponding steering gates are positioned above the floating gates. The select gate is formed above the steering gates and also overlies the channel itself.
In an array of cells the select gates of the memory cells along a row are coupled to form a word line along that row. The diffusions in different rows are aligned and coupled to form bit lines across the rows. Also, the steering gates in different rows are aligned and coupled to form steering lines. A recent design of a memory cell array is described in U.S. Pat. No. 6,151,248, granted to E. Harari, which is incorporated herein by this reference in its entirety.
Flash EEPROM memories hold some key advantages over other types of memory systems. One of these advantages is the non-volatile nature of the data storage, making these systems prime candidate for a wide variety of applications, including digital cameras, recording music and utilization in mobile communications.
A characteristic of flash memory systems is, however, the relatively long time it takes to program the cells. Programming can take as long as 10-1000 microseconds, longer than, for example, present day DRAMs.
Many cells are programmed simultaneously in the memory systems. The cells of the array are selected for programming in a certain scheme. The speed of the programming is influenced by this scheme. In some arrays the simultaneous programming is performed, for example, on every fourth, or every seventh cell only. Therefore these schemes require four or seven programming cycles to program all the cells of the array, respectively.
Thus programming schemes which program memory arrays in fewer cycles are desired.
The programming speed is affected also by the operating speed of the individual circuit elements involved. For example, if the input/output circuitry is slower than the internal array circuitry, the overall operating speed of the memory system will be restricted by the speed of the input/output circuitry. The input/output circuitry can be slow, for example, because relatively high voltages have to be applied to program some of the arrays. In order to handle higher voltages, the thickness of the oxide layers of the programming circuit elements has to be increased. This in turn slows down the operating speed of these circuit elements.
Therefore improvements in programming voltage assignments in the memory arrays are desired.
Another aspect of the quality of flash EEPROM related products is their expected lifetime. The lifetime is influenced by several factors. One of them is associated with the relatively high voltages needed to program the memory cells. Every time these relatively high programming voltages are applied, some degree of wear occurs in the memory cell, thereby limiting the useful lifetime of the memory cell.
Thus programming schemes reducing the number of instances, when high programming voltages have to be applied have the potential of extending the lifetime of flash memory based products.
Briefly and generally, the cells of a memory array are programmed in a new, pair wise programming scheme. The cells are programmed by the application of a data-independent high voltage and a data-dependent low voltage. This novel programming scheme and voltage assignment has the advantage of increasing the speed of the programming and the lifetime of the memory cell array.
According to one aspect of the invention a new programming scheme is introduced. The cells of a memory cell array are programmed in a novel, pair wise scheme. The programmed pairs of cells are separated by at least one memory cell, reducing the possibility of interference between the pairs during programming. This scheme is capable of programming all cells of the array in three programming cycles. Previous methods, which program every fourth or every seventh memory cell of an array in one cycle, are only capable of programming all cells of the array in four or seven cycles, respectively.
According to another aspect of the invention new programming voltage assignments are introduced. The memory cells of an array are typically associated with two bit lines. In existing memory systems a relatively high voltage is applied to one of the cell""s bit lines, if the cell is to be programmed, while applying a low voltage to the second bit line of the cell irrespective whether the cell is to be programmed or not. The programming circuit elements, including input/output circuitry, buses, and drivers, have to be capable of handling these relatively high voltages. This is achieved, among others, by increasing the thickness of the oxide layers of the involved semiconductor devices. Devices with thicker oxide layers, however, operate slower, eventually reducing the speed of reading of the whole array.
The novel programming voltage assignments according to an aspect of the invention eliminate the necessity of thicker semiconductor layers in the programming circuit elements because the memory cell is programmed by applying the relatively high voltage to one of the bit lines irrespective whether the cell is to be programmed or not. The programming of the cell is controlled instead by the voltage applied to the second bit line of the cell. Both the programming and the non-programming voltages, applied to the second bit line, are lower than the relatively high voltage applied to the first bit line. Therefore the programming circuit elements, including the input/output circuitry, buses, and drivers, can all operate at lower voltages. This allows for utilizing thinner oxide layers, thus enhancing the operating speed of the programming circuit elements and eventually the overall performance of the circuit.
The lifetime of memory cells is also affected by the above programming scheme and programming voltage assignments. As mentioned above, every time a high voltage is applied to a bit line, some degree of wear occurs, shortening the lifetime of the cell. In the pair wise programming scheme, however, the application of the high programming voltage to one bit line programs two memory cells. Therefore high programming voltages have to be applied only half as often as in previous schemes to program all the cells of the array, increasing the lifetime of the memory system.